Some integrated circuits decrease their associated delay times by doubling their data rates. Typically, to support data rate doubling a single phase clock input is split into true and complement clocks by a clock generator. These two internal clocks allow data sampling to occur on both the rising and falling edges of the single phase clock input. FIG. 1 illustrates a prior art Double Data Rate input Receiver (DRR) 26, which receives true and complement clocks from Clock Generator 20. From the single phase clock, the CLK signal, Clock Generator 20 generates the internal true and complement clock signals, which are labeled CLKL and CLKB, respectively. To promote satisfactory receive timing margins, the CLKL and CLKB signals should be 180.degree. apart in phase. A Duty Cycle Correction Circuit may be used to force the CLKL and CLKB signals into this relationship.
FIG. 2 illustrates a prior art Duty Cycle Correction Circuit 30 coupled to a Clock Generator 20. The complementary clock signals, CLKL and CLKB, are input to the Duty Cycle Correction Circuit 30. Working in concert, Duty Cycle Correction Circuit 30 and Adjustor Circuit 40 set the duty cycle of the CLK signal such that the two cross points of the CLKL and CLKB signals are separated by half the cycle time. In contrast, DRR 26 is sensitive only to the rising edges of the CLKL and CLKB signals; for optimal timing, these rising edges should be separated in phase by 180 degrees. The DCCV and DCCVB signals allow Adjustor Circuit 40 to modify the duty cycle of the CLK signal. Measuring the differences between the CLKL and CLKB signals, the Duty Cycle Correction Circuit 30 is sensitive to the cross points of the CLKL and CLKB signals. In contrast, DRR 26 is sensitive only to the rising edges of the CLKL and CLKB signals. Thus, DRR 26 and Duty Cycle Correction Circuit (DCCC) 30 use different definitions of duty cycle.
FIG. 3 plots the CLKL and CLKB signals and indicates their duty cycles using a number of definitions. Generally, duty cycle is defined as a signal's high time divided by the sum of the signal's high and low time; i.e., the total cycle time. No disagreement exists as to what constitutes a signal's total cycle time; however, there are a number of competing definitions of cycle high time. In FIG. 3 "t.sub.1 " indicates the high time of the CLKL signal as the time between when the rising edge of the CLKL signal crosses the falling edge of the CLKB signal and when the falling edge of the CLKL signal intersects the rising edge of the CLKB signal. Thus, t.sub.1 represents the cross-point high time to which the DCCC 30 is sensitive. In FIG. 3 "t.sub.2 " indicates the high time of the CLKL signal as the time from when the voltage of the rising edge of the CLKL signal exceeds a selected threshold level to when the voltage of the rising edge of the CLKB signal exceeds the selected threshold level. Thus, t.sub.2 represents the rising edge high time to which the DRR 26 is sensitive. Within an integrated circuit using a DRR 26 and a Duty Cycle Correction Circuit 30 even a small difference between the cross-point high time and the rising edge high time substantially impacts receive time margins. Thus, a need exists for a converter circuit to generate a pair of signals whose cross-point duty cycle is equal to the midpoint duty cycle of the CLKL and CLKB signals. Inserted between a DRR 26 and a Duty Cycle Correction Circuit 30, such a converter circuit would improve receive time margins.